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| oki semiconducto r pedl9204-02 issue date: oct. 12, 2004 ML9204-XX preliminary 5 7 dot character 24-digit 2-line display controller/driver with character ram (built-in key scan) 1/41 general description the ML9204-XX is a 5 7 dot matrix type vacuum fluorescent display tube controller driver ic which displays characters, numerics and symbols of a maximum of 24 digits 2 lines. dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller. a display system is easily realized by internal rom and ram for character display. built-in key scan for 3-channel encoder type rotary switch and 5 6 matrix key switch allow the user to receive each switch input. the ML9204-XX has low power consumption since it is made by cmos process technology. ?01 is available as a general-purpose code. custom codes are provided on customer?s request. features ? logic power supply (v dd ) : 3.3 v10% or 5.0 v10% ? vfd tube drive power supply (v seg , v com ) : 20 to 60 v ? vfd driver output current (vfd driver output can be connected directly to the vfd tube. no pull-down resistor is required.) ? segment driver (sega1 to a35, segb1 to b35) only one driver output is high : ?5 ma (v seg = 60 v) all the driver outputs are high : ?350 ma (v seg = 60 v) ? segment driver (ada, adb) : ?15 ma (v seg = 60 v) ? grid driver (com1 to 24) : ?25 ma (v com = 60 v) ? content of display sega1 to sega35 and ada ? cgrom_a : 5 7 dots 240 types (character data) ? cgram_a : 5 7 dots 16 types (character data) ? adram_a : 24 (display digit) 1 bit (symbol data; can be used for a cursor.) ? dcram_a : 24 (display digit) 8 bits (register for character data display) segb1 to segb35 and adb ? cgrom_b : 5 7 dots 240 types (character data) ? cgram_b : 5 7 dots 16 types (character data) ? adram_b : 24 (display digit) 1 bit (symbol data; can be used for a cursor.) ? dcram_b : 24 (display digit) 8 bits (register for character data display) ? display control function ? gcram : simultaneous output of com1 to 24 can be set in 1 grid. ? display digits : 1 to 24 digits (9- to 24-bit arbitrary setting) ? display duty (brightness adjustment) : 0/1024 to 960/1024 stages ? all lights on/off ? 5 interfaces with microcontroller:di/o, cs , cp , reset , int ? built-in key scan circuit for 5 6 matrix key switch ? built-in key scan circuit for 3-channel encoder type rotary switch ? built-in oscillation circuit crystal oscillation or ceramic oscillation: 4.0 mhz (typ) ? standby function inhibiting the oscillator circuit provides low power consumption. ? package options: 128-pin plastic qfp (qfp128-p-1420-0.50-k) (ML9204-XXga)
pedl9204-02 oki semiconductor ML9204-XX 2/41 block diagram v com v dd d-gnd r ese t cp cs osc0 osc1 sega1 sega35 a d a com1 com 24 dcram_a 24w 8b cgrom_a 240w 35b cgram_a 16w 35b adram_b 24w 1b command decoder control circuit timing generator 1 oscillator digit control duty control grid driver segment driver write address counter read address counter address selector segment driver segb1 segb35 a db dcram_b 24w 8b cgrom_b 240w 35b cgram_b 16w 35b adram_b 24w 1b segment driver segment driver timing generator 2 l-gnd 5 x 6 key scan and encoder switch interface int b3 a3 b2 a2 b1 a1 c ol 6 c ol 1 row5 row1 gcram 24w 24b v seg di/o 8bit shift register pedl9204-02 oki semiconductor ML9204-XX 3/41 pin configuration (top view) 108 107 106 105 104 103 segb27 segb28 segb29 segb30 segb31 segb32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 1 09 segb7 segb8 segb9 segb10 segb11 segb12 segb13 segb14 segb15 segb16 segb17 segb18 segb19 segb20 segb21 segb22 segb23 segb24 segb25 segb26 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 sega7 sega8 sega9 sega10 seg a 11 sega12 sega13 sega14 sega15 sega16 sega17 sega18 sega19 s e g a2 0 sega21 sega22 sega23 sega24 sega25 sega26 59 sega27 60 sega28 61 sega29 62 sega30 63 sega31 64 sega32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 segb6 segb5 segb4 segb3 segb2 v com com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 segb1 31 32 33 34 35 36 37 38 com24 v com seg a 2 sega3 seg a 4 seg a 5 sega6 sega1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 a db segb33 segb34 segb35 v seg d-gnd v dd int di/o cp cs r ese t b3 a3 b2 a2 b1 a1 c ol 6 c ol 5 c ol 4 c ol 3 c ol 2 c ol 1 row5 row4 row3 row2 row1 osc1 a d a 72 71 70 69 68 67 66 65 osc0 l-gnd d-gnd v seg sega35 sega34 sega33 128-pin plastic qfp pedl9204-02 oki semiconductor ML9204-XX 4/41 pin description pin symbol type connects to description 33 to 67 sega1 to a35 1 to 6 100 to 128 segb1 to b35 o vfd tube anode electrode vfd tube anode electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh < ?5 ma 8 to 31 com1 to 24 o vfd tube grid electrode vfd tube grid electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh < ?25 ma 68 ada 99 adb o vfd tube anode electrode vfd tube anode electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh < ?15 ma 96 v dd 71 l-gnd 7,32 v com 69,98 v seg 70,97 d-gnd ? power supply v dd -l-gnd are power supplies for internal logic. v com -d-gnd are power supplies for driving vfd tube grid. v com -d-gnd are power supplies for driving vfd tube anode. use the same power supply for l-gnd and d-gnd. 94 di/o i/o micro controller serial data input-output (positive logic). data is input and output to sift register synchronized with the rise of shift clock. when inputting data input from the lsb. 93 cp l micro controller shift clock input. serial data is shifted on the rising edge of cp . 92 cs l micro controller chip select input. serial data transfer is disabled when cs pin is ?h? level. 95 int o micro controller output pin for interrupt signal to micro controller. when depression or release of key matrix switch is detected, key scanning starts and when 1 cycle is completed, this pin becomes high level. upon receiving encoder type rotary switch input, this pin becomes high level. the int pin remains at high level until the key scan stop mode is selected.. 85,86 87,88 89,90 a1,b1 a2,b2 a3,b3 l rotary switch encoder type rotary switch input pins. all inputs possess chattering absorption function of 256us period. those inputs must be tied to ground when they are not used. 79 to 84 col 1 to 6 i key matrix input pins for return signal from key matrix with built-in pull-up resister. when input is low level, the key matrix switch is regarded as being pressed. dose not have chattering absorption function. pedl9204-02 oki semiconductor ML9204-XX 5/41 74 to 78 row1 to 5 o key matrix key matrix scan signal output pins. normally low level is output. key scanning starts by detecting depression or release of key matrix switch and continues until selection of key scan stop mode. when key scan stop mode is selected, all outputs of row1 to 5 return to low level. 91 reset l micro controller reset input. ?low? initializes all the functions. initial status is as follows. ? address of each ram .............. address ?00?h ? data of each ram ................... content is undefined ? display digit............................. 24 digits ? brightness adjustment ............. 0/ 1024 ? all lights on or off ................ off mode ? row1 to 5 .............................. becomes low level ? int.......................................... becomes low level 72 osc0 l 73 osc1 o crystal or ceramic resonator pins for self-oscillation. (do not apply external clocks to these pins.) connect these pins to the crystal and capacitors or to the ceramic resonator and capacitors. the target oscillation frequency is 4.0mhz. (the device has an internal feedback resister.) v dd typical 3.3v 1mohm 5.0v 0.4mohm * for information regarding the oscillator contact the manufacturer of the osc illator. * as regards the circuit, refer to the application circuit. pedl9204-02 oki semiconductor ML9204-XX 6/41 absolute maximum ratings parameter symbol condition rating unit supply voltage (1) v dd ? ?0.3 to +6.5 v v seg ? ?0.3 to +70 v supply voltage (2) v com ? ?0.3 to +70 v input voltage v in ? ?0.3 to v dd +0.3 v power dissipation p d ta 85c 470 *1) mw storage temperature t stg ? ?55 to +150 c l o1 com1 to com24 ?50 to +2.0 ma l o2 ada, adb ?30 to +2.0 ma l o3 sega1 to sega35, segb1 to segb35 ?10 to +2.0 ma output current i o4 row1 to 5 / int ?2.0 to +2.0 ma *1) when use two or more com, be careful of the following things. the junction temperature which can be found by the following formula does not exceed 120. tj = (px 85c /w)+ta (p is the maximum power consumption of ic.) recommended operating conditions parameter symbol condition min. typ. max. unit when the power supply voltage is 5.0 v (typ.) 4.5 5.0 5.5 v supply voltage (1) v dd when the power supply voltage is 3.3 v (typ.) 3.0 3.3 3.6 v v seg ? 20 ? 60 v supply voltage (2) v com ? 20 ? 60 v operating frequency f osc oscillation 3.5 4.0 4.5 mhz frame frequency f fr digit = 1 to 24, oscillation 142 163 183 hz operating temperature t op ? ?40 ? +85 c pedl9204-02 oki semiconductor ML9204-XX 7/41 electrical ch aracteristics dc characteristics (v dd = 5.0 v10%) (v dd = 5.0 v10%, v seg and v com = 20 to 60 v, ta = ?40 to +85c, unless otherwise specified) parameter symbol applied pin condition min. max. unit high level input voltage v ih *1 v dd = 5.0 v10% 0.7 v dd ? v low level input voltage v il *1 v dd = 5.0 v10% ? 0.3 v dd v high level input current i ih *1 v ih = v dd ?1.0 +1.0 a i il1 *2 v il = 0.0 v ?1.0 +1.0 a low level input current i il2 col1 to 6 v dd = 5.0 v10%, v il = 0.0 v ?450 ?100 a v oh1 com1 to 24 v com = 60 v, i oh1 = ?25 ma v com ? 2.0 ? v v oh2 ada, adb v seg = 60 v, i oh2 = ?15 ma v seg ? 2.0 ? v v oh3 sega1 to a35 segb1 to b35 v seg = 60 v, i oh3 = ?5 ma v seg ? 2.0 ? v high level output voltage v oh4 int, row1 to 5 v dd = 5.0 v10%, i oh4 = ?450 a v dd ? 0.2 ? v v ol1 *3 ? ? 1.0 v low level output voltage v ol2 int, row1 to 5 v dd =5.0 v10%, i ol2 = 450 a ? 0.2 v i dd1 v dd v dd = 5.0 v10%, f osc = 4.0 mhz ? 6.0 ma i disp1 all output lights on ? 1.0 ma supply current (1) i disp2 v seg, v com f osc = 4.0 mhz, no load all output lights off ? 200 a i dds v dd ? 1.0 a supply current (2) i disps v seg, v com in standby mode ? 20.0 a *1) cs , cp , di/o, reset , col 1 to 6 *2) cs , cp , di/o, reset *3) sega1 to a35, segb1 to b35, ada, adb, com1 to 24 pedl9204-02 oki semiconductor ML9204-XX 8/41 dc characteristics (v dd = 3.3 v10%) (v dd = 3.3 v10%, v seg and v com = 20 to 60 v, ta = ?40 to +85c, unless otherwise specified) parameter symbol applied pin condition min. max. unit high level input voltage v ih *1 v dd = 3.3 v10% 0.8 v dd ? v low level input voltage v il *1 v dd = 3.3 v10% ? 0.2 v dd v high level input current i ih *1 v ih = v dd ?1.0 +1.0 a i il1 *2 v il = 0.0 v ?1.0 +1.0 a low level input current i il3 col1 to 6 v dd = 3.3 v10%, v il = 0.0 v ?120 ?25 a v oh1 com1 to 24 v com = 60 v, i oh1 = ?25 ma v com ? 2.0 ? v v oh2 ada, adb v seg = 60 v, i oh2 = ?15 ma v seg ? 2.0 ? v v oh3 sega1 to a35 segb1 to b35 v seg = 60 v, i oh3 = ?5 ma v seg ? 2.0 ? v high level output voltage v oh5 int, row1 to 5 v dd = 3.3 v10%, i oh5 = ?120 a v dd ? 0.2 ? v v ol1 *3 ? ? 1.0 v low level output voltage v ol2 int, row1 to 5 v dd = 3.3 v10%, i ol3 = 120 a ? 0.2 v i dd2 v dd v dd = 3.3 v10%, f osc = 4.0 mhz ? 4.0 ma i disp1 all output lights on ? 1.0 ma supply current (1) i disp2 v seg, v com f osc = 4.0 mhz, no load all output lights off ? 200 a i dds v dd ? 1.0 a supply current (2) i disps v seg, v com in standby mode ? 20.0 a *1) cs , cp , di/o, reset , col 1 to 6 *2) cs , cp , di/o, reset *3) sega1 to a35, segb1 to b35, ada, adb, com1 to 24 pedl9204-02 oki semiconductor ML9204-XX 9/41 ac characteristics (v dd = 5.0 v10%, or v dd = 3.3 v10%,v seg and v com = 20 to 60 v, t a = ?40 to +85c unless otherwise specified) parameter symbol condition min. max. unit cp frequency f c ? ? 2.0 mhz cp pulse width t cw ? 200 ? ns d/a setup time t ds ? 200 ? ns d/a hold time t dh ? 200 ? ns cs setup time t css ? 200 ? ns cs hold time t csh oscillating state 8 ? s cs wait time t csw ? 200 ? ns data processing time t doff oscillating state 4 ? s reset pulse width t wres when reset signal is input from microcontroller etc. externally 200 ? ns reset time t rson ? t oscon ? d/a wait time t rsoff ? 200 ? ns t r t r = 20 to 80% ? 2.0 s all output slew rate t f c l = 100 pf t f = 80 to 20% ? 2.0 s osc duty ratio du osc ? 40 60 % oscillation rise time t oscon ? *1 *1 t oscon (oscillation rise time) differs with the oscillator pin used. as regards osc illation rise time, refer to the data of oscillator used. key scan characteristics (v dd = 5.0v10%, or v dd = 3.3v10%, v seg and v com = 20 to 60 v, t a = ?40 to +85c unless otherwise specified) parameter symbol condition min. typ. max. unit key scan time t scan 142.2 160 182.8 s key scan pulse width t wscan f osc = 3.5 to 4.5 mhz 28.4 32 36.6 s rotary switch characteristics (v dd = 5.0v10%, or v dd = 3.3v10%, v seg and v com = 20 to 60 v, t a = ?40 to +85c unless otherwise specified) parameter symbol condition min. typ. max. unit phase input time t abw phase input fixed time t abh f osc = 3.5 to 4.5 mhz 1.2 ? ? ms pedl9204-02 oki semiconductor ML9204-XX 10/41 timing diagrams symbol v dd = 5.0 v 10% v dd = 3.0 v 10% v ih 0.7 v dd 0.8 v dd v il 0.3 v dd 0.2 v dd data input timing data output timing output timing 5) osc timing c s c p di/o (input) t css t ds t dh t doff t cw valid valid valid valid v ih v ih v il v il v ih v il 1/f c t cw t csh t csw cs cp di/o t css t csh ?v ih ?v il ?v ih ?v il ?v ih ?v il (output) valid valid t pd t pd valid t pd t pd valid valid ? 0.8 ( v se g , v com ) t f t r ?0.2 (v seg, v com ) all output driver -0.5vdd du osc =bx100/(a+b) osc1 a b pedl9204-02 oki semiconductor ML9204-XX 11/41 standby mode release timing reset timing * after a vdd injection should surely input a reset signal. key scan timing c s c p osc0 ?v ih ? v il 200nsec or more 0.9vp-p vp-p (stationary state oscillation level) di/o valid ?v ih ? v il ?v ih ? v il t rson t oscon v dd r ese t di/o t rson ?0.8 v dd ?v ih ?0.0 v ?v il t rsoff t wres valid ?v ih ? v il row1 row5 row2 row3 row4 t scan t wscan pedl9204-02 oki semiconductor ML9204-XX 12/41 rotary switch input timing digit output timing (24-digit,960/1024-duty) a b t abh t abw t abh t abw t abw com1 com2 com3 com4 com5 com20 com21 com22 com23 com24 a da, adb, sega1~ a 35, segb1~b35 d-gnd t 1 = 24576t t 2 = 960t t 3 = 64t frame cycle display blank timing v com d-gnd v seg *: t = 1/f osc (f osc = 4.0 mhz : t 1 = 6.144ms) (f osc = 4.0 mhz : t 2 = 240s) (f osc = 4.0 mhz : t 3 = 16s) pedl9204-02 oki semiconductor ML9204-XX 13/41 functional description commands list lsb 1st byte msb lsb 2nd byte msb command b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 1 dcram_a data write * * * * 1000c0c1c2c3c4 c5 c6 c7 c0 c5 c10 c15 c20 c25 c30 * 2nd byte c1 c6 c11 c16 c21 c26 c31 * 3rd byte c2 c7 c12 c17 c22 c27 c32 * 4th byte c3 c8 c13 c18 c23 c28 c33 * 5th byte 2 cgram_a data write0 0 0 00100 c4 c9 c14 c19 c24 c29 c34 * 6th byte 3 adram_a data write * * * *1100c0* * * * * * * c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 4 gcram data write * * * *0010 c16 c17 c18 c19 c20 c21 c22 c23 5 display duty set d0 d1 * *1010d2d3d4d5d6 d7 d8 d9 6 number of digits set k0 k1 k2 k30110 7 all lights on/off l h * *1110 9 dcram_b data write * * * * 1001c0c1c2c3c4 c5 c6 c7 c0 c5 c10 c15 c20 c25 c30 * 2nd byte c1 c6 c11 c16 c21 c26 c31 * 3rd byte c2 c7 c12 c17 c22 c27 c32 * 4th byte c3 c8 c13 c18 c23 c28 c33 * 5th byte a cgram_b data write0 0 0 00101 c4 c9 c14 c19 c24 c29 c34 * 6th byte b adram_b data write * * * *1101c0* * * * * * * c key scan stop * * * *0011 d key data output * * * *1011 refer to item d of command and function description. f standby mode * * * * 1111 0 test mode(note) 0000 when data is written to ram (dcram, cgram, adram, and gcram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. * : don?t care xn : address specification for each ram cn : character code specification for each ram dn : display duty specification kn : number of digits specification h : all lights on instruction l : all lights off instruction note: the test mode is used for inspection before shipment. it is not a user function. the user cannot use this command. enter commands 1 to 7, 9 to d, and f alone in the way described on the next page and the following pages. (the operation of this device cannot be guaranteed if other commands are used. pedl9204-02 oki semiconductor ML9204-XX 14/41 positional relationship between segn and adn (one digit) c0 c0 sega1 c5 sega6 c10 sega11 c15 sega16 c20 sega21 c25 sega26 c30 sega31 c1 sega2 c6 sega7 c11 sega12 c16 sega17 c21 sega22 c26 sega27 c31 sega32 c2 sega3 c7 sega8 c12 sega13 c17 sega18 c22 sega23 c27 sega28 c32 sega33 c3 sega4 c8 sega9 c13 sega14 c18 sega19 c23 sega24 c28 sega29 c33 sega34 c4 sega5 c9 sega10 c14 sega15 c19 sega20 c24 sega25 c29 sega30 c34 sega35 corresponds to the 2nd byte of the adram_a data write command. corresponds to the 6th byte of the cgram_a data write command. corresponds to the 5th byte of the cgram_a data write command. ada corresponds to the 4th byte of the cgram_a data write command. corresponds to the 3rd byte of the cgram_a data write command. corresponds to the 2nd byte of the cgram_a data write command. c0 c0 segb1 c5 segb6 c10 segb11 c15 segb16 c20 segb21 c25 segb26 c30 segb31 c1 segb2 c6 segb7 c11 segb12 c16 segb17 c21 segb22 c26 segb27 c31 segb32 c2 segb3 c7 segb8 c12 segb13 c17 segb18 c22 segb23 c27 segb28 c32 segb33 c3 segb4 c8 segb9 c13 segb14 c18 segb19 c23 segb24 c28 segb29 c33 segb34 c4 segb5 c9 segb10 c14 segb15 c19 segb20 c24 segb25 c29 segb30 c34 segb35 corresponds to the 2nd byte of the adram_b data write command. corresponds to the 6th byte of the cgram_b data write command. corresponds to the 5th byte of the cgram_b data write command. adb corresponds to the 4th byte of the cgram_b data write command. corresponds to the 3rd byte of the cgram_b data write command. corresponds to the 2nd byte of the cgram_b data write command. comn pedl9204-02 oki semiconductor ML9204-XX 15/41 data transfer method and command write method display control command and data are written by an 8-bit serial transfer. write timing is shown in the figure below. setting the cs pin to ?low? level enables a data transfer. data is 8 bits and is sequentially input into the di/o pin from lsb (lsb first). as shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the cp pin. if 8-bit data is input, internal load signals are automatically generated and data is written to each register and ram. therefore it is not necessary to input load signals from the outside. setting the cs pin to ?high? disables data transfer. data input from the point when the cs pin changes from ?high? to ?low? is recognized in 8-bit units. * when data is written to ram (dcram, adram, cgram, gcram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. t doff lsb c s c p msb 1st byte lsb msb 2nd byte command and address data t csh lsb msb 3rd byte character code data of the next address character code data when data is written to dcram* da b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 pedl9204-02 oki semiconductor ML9204-XX 16/41 data outputting and command writing in an operation to read key scan data, when cs goes ?low? after key data output mode is entered, the di/o pin changes modes to output and key data is output in synchronization with the rise of shift lock. the waveforms to read key data are shown blow. the di/o pin enters the input mode when the cs pin is set to ?high? after key data is output. keyscan stop data output (42-bit) key data output mode c p c s t csh lsb msb lsb msb di/o b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 valid reset function reset is executed when the reset pin is set to ?l?, (when turning power on, for example) and initializes all functions. initial status is as follows. ? address of each ram..................... address ?00?h ? data of each ram .......................... a ll contents are undefined ? display digit ................................... 24 digits ? brightness ad justment..................... 0/ 1024 ? all display lights on or off .......... off mode ? segment output............................... all se gment outputs go ?low? ? ad output....................................... all ad outputs go ?low? ? row1 to 5...................................... all ro w outputs go ?low? ? int................................................. int goes ?low.? be sure to execute the reset operation when turning power on and set again according to ?setting flowchart? after reset. pedl9204-02 oki semiconductor ML9204-XX 17/41 description of commands and functions 1,9. dcram data write (writes the character code of cgrom and cgram.) dcram (data control ram) has a 5-bit address to store character code of cgrom and cgram. the character code specified by dcram is converted to a 5 7 dot matrix character pattern via cgrom or cgram. (the dcram can store 24 characters.) [command format] to specify the character code of cgrom and cgram continuously to the next address, specify only character code as follows. the addresses of dcram are automatically incremented. specification of an address is unnecessary. a character code setup of cgrom to 24-digit and cgram is completion in the above work. furthermore, you have to specify the character codes of a dummy to be dcram and 18h-1fh to perform a character code setup from dcram address 00h continuously. (in order to carry out the increment of the address of dcram automatically and to set a dcram address to 00h.) * * * * 1 0 0 0/1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : selects dcram data write mode : specifies character code of cgrom and cgram (written into dcram address 00h) 0: select dcram_a 1: select dcram_b c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : specifies character code of cgrom and cgram (written into dcram address 01h) : specifies character code of cgrom and cgram (written into dcram address 02h) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (25th) lsb msb : specifies character code of cgrom and cgram (written into dcram address 17h) c0 c1 c2 c3 c4 c5 c6 c7 pedl9204-02 oki semiconductor ML9204-XX 18/41 c0 (lsb) to c7 (msb): character code of cgrom and cgram (8 bits: 256 characters) * : don?t care [com positions and set dcram addresses] dcram address (hex) com dcram address (hex) com dcram address (hex) com 00 com1 0c com13 18 dummy 01 com2 0d com14 19 dummy 02 com3 0e com15 1a dummy 03 com4 0f com16 1b dummy 04 com5 10 com17 1c dummy 05 com6 11 com18 1d dummy 06 com7 12 com19 1e dummy 07 com8 13 com20 1f dummy 08 com9 14 com21 09 com10 15 com22 0a com11 16 com23 0b com12 17 com24 cgrom of a dummy and the character code of cgram are specified. (it is not written in a dcram address.) character code of cgrom and cgram is specified. (dcram address 00h are rewritten.) 8 times enforcement c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (26th) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (33th) lsb msb : : b0 b1 b2 b3 b4 b5 b6 b7 2nd byte lsb msb : c0 c1 c2 c3 c4 c5 c6 c7 (34th) cgrom of a dummy and the character code of cgram are specified. (it is not written in a dcram address.) dummy is put in to set up a dcram address from 00h continuously. pedl9204-02 oki semiconductor ML9204-XX 19/41 2,a. cgram data write (cgram writes character pattern data.) cgram (character generator ram) has a 4-bit address to store 5x 7 dot matrix character patterns. a character pattern stored in cgram can be displayed by specifying the character code (address) by dcrom. the address of cgram is assigned to 00h to 0fh. (all the other addresses are the cgrom addresses.) (the cgram can store 16 types of character patterns.) [command format] to specify character pattern data continuously to the next address, specify only character pattern data as follows. the addresses of cgram are automatically incremented. specification of an address is unnecessary. the 2nd to 6th byte (character pattern data) are regarded as one data item, so 200 ns is sufficient for t doff time between bytes. c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : specifies 1st column data (rewritten into cgram address 00h) c1 c6 c11 c16 c21 c26 c31 * b0 b1 b2 b3 b4 b5 b6 b7 3rd byte (3rd) lsb msb : specifies 2nd column data (rewritten into cgram address 00h) 0 0 0 0 0 1 0 0/1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects cgram data write mode c2 c7 c12 c17 c22 c27 c32 * b0 b1 b2 b3 b4 b5 b6 b7 4th byte (4th) lsb msb : specifies 3rd column data (rewritten into cgram address 00h) c3 c8 c13 c18 c23 c28 c33 * b0 b1 b2 b3 b4 b5 b6 b7 5th byte (5th) lsb msb : specifies 4th column data (rewritten into cgram address 00h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (6th) lsb msb : specifies 5th column data (rewritten into cgram address 00h) 0: select cgram_a 1: select cgram_b pedl9204-02 oki semiconductor ML9204-XX 20/41 x0 (lsb) to x3 (msb) : cgram addresses (4 bits: 16 characters) c0 (lsb) to c34 (msb) : character pattern data (35 bits: 35 outputs per digit) * : don't care c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (7th) lsb msb : specifies 1st column data (rewritten into cgram address 01h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (11th) lsb msb : specifies 5th column data (rewritten into cgram address 01h) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (12th) lsb msb : specifies 1st column data (rewritten into cgram address 02h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (16th) lsb msb : specifies 5th column data (rewritten into cgram address 02h) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (77th) lsb msb : specifies 1st column data (rewritten into cgram address 0fh) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (81th) lsb msb : specifies 5th column data (rewritten into cgram address 0fh) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (82th) lsb msb : specifies 1st column data (rewritten into cgram address 00h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (86th) lsb msb : specifies 5th column data (rewritten into cgram address 00h) pedl9204-02 oki semiconductor ML9204-XX 21/41 [cgrom addresses and set cgram addresses] refer to rom code tables. hex x0 x1 x2 x3 cgrom address hex x0 x1 x2 x3 cgrom address 00 0 0 0 0 ram00 (00000000b) 08 0 0 0 1 ram08 (00001000b) 01 1 0 0 0 ram01 (00000001b) 09 1 0 0 1 ram09 (00001001b) 02 0 1 0 0 ram02 (00000010b) 0a 0 1 0 1 ram0a (00001010b) 03 1 1 0 0 ram03 (00000011b) 0b 1 1 0 1 ram0b (00001011b) 04 0 0 1 0 ram04 (00000100b) 0c 0 0 1 1 ram0c (00001100b) 05 1 0 1 0 ram05 (00000101b) 0d 1 0 1 1 ram0d (00001101b) 06 0 1 1 0 ram06 (00000110b) 0e 0 1 1 1 ram0e (00001110b) 07 1 1 1 0 ram07 (00000111b) 0f 1 1 1 1 ram0f (00001111b) positional relationship between the output area of cgram note: cgrom_a and cgrom_b (character generator rom a, b) have an 8-bit address to generate 5 x 7 dot matrix character patterns. each of cgrom_a and cgrom_b can store 240 types of character patterns. the contents of cgrom_a and cgrom_b can be set separately. general-purpose code -01 is available (see rom code tables) and custom codes are provided on customer's request. c0 segn1 c5 segn6 c10 segn11 c15 segn16 c20 segn21 c25 segn26 c30 segn31 c1 segn2 c6 segn7 c11 segn12 c16 segn17 c21 segn22 c26 segn27 c31 segn32 c2 segn3 c7 segn8 c12 segn13 c17 segn18 c22 segn23 c27 segn28 c32 segn33 c3 segn4 c8 segn9 c13 segn14 c18 segn19 c23 segn24 c28 segn29 c33 segn34 c4 segn5 c9 segn10 c14 segn15 c19 segn20 c24 segn25 c29 segn30 c34 segn35 area that corresponds to 2nd byte (1st column) (input 1000001*b) area that corresponds to 3rd byte (2nd column) (input 1010101*b) area that corresponds to 4th byte (3rd column) (input 1001001*b) area that corresponds to 5th byte (4th column) (input 1100011*b) area that corresponds to 6th byte (5th column) (input 1100011*b) c5 segn6 c10 segn11 c15 segn16 c20 segn21 c25 segn26 c11 segn12 c16 segn17 c21 segn22 c7 segn8 c17 segn18 c27 segn28 c8 segn9 c13 segn14 c23 segn24 c28 segn29 c14 segn15 c19 segn20 c24 segn25 pedl9204-02 oki semiconductor ML9204-XX 22/41 3,b. adram data write (adram writes symbol data) adram (additional data ram) has a 1-bit address to store symbol data. symbol data specified by adram is directly output without cgrom and cgram. (the adram can store 1 type of symbol patterns for each digit.) the terminal to which the contents of adram are output can be used as a cursor. [command format] to specify symbol data continuously to the next address, specify only character data as follows. the address of adram is automatically incremented. specification of addresses is unnecessary. a character code setup of 24-digit is completion in the above work. furthermore, you have to specify the character codes of a dummy to be adram and 18h-1fh to perform a character code setup from adram address 00h continuously. (in order to carry out the increment of the address of adram automatically and to set a adram address to 00h.) c0 * * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : sets symbol data (written into adram address 00h) * * * * 1 1 0 0/1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects adram data write mode 0: select adram_a 1: select adram_b c0 * * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb : sets symbol data (written into adram address 01h) c0 * * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : sets symbol data (written into adram address 02h) c0 * * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (25th) lsb msb : sets symbol data (written into adram address 17h) pedl9204-02 oki semiconductor ML9204-XX 23/41 c0 : symbol data (1 bit: 1-symbol data per digit) * : don?t care [com positions and adram addresses] adram address (hex) com adram address (hex) com adram address (hex) com 00 com1 0c com13 18 dammy 01 com2 0d com14 19 dammy 02 com3 0e com15 1a dammy 03 com4 0f com16 1b dammy 04 com5 10 com17 1c dammy 05 com6 11 com18 1d dammy 06 com7 12 com19 1e dammy 07 com8 13 com20 1f dammy 08 com9 14 com21 09 com10 15 com22 0a com11 16 com23 0b com12 17 com24 c0 * * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (26th) lsb msb : the sign data of a dummy is specified. (it is not written in an adram address.) c0 * * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (33th) lsb msb : c0 * * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (34th) lsb msb : the sign data of a dummy is specified. (it is not written in an adram address.) the sign data of a dummy is specified. (adram address 00h are rewritten.) dummy is put in to set up a adram address from 00h continuously. pedl9204-02 oki semiconductor ML9204-XX 24/41 4. gcram data write (writes data by the number of com outputs for digits) gcram (grid control ram) has a 5-bit address to control the number of com outputs for digits. gcram outputs specified data directly to comn, allowing com outputs to be controlled arbitrarily. it is also possible to supply a large current by connecting a plur ality of coms ou tside the ml9204. for example, when com23 and com24 are connected, the ml9204 has 23 display digits. in this case, the user specifies ?23? as the number of display digits. write grid data at gcram addresses 00h and later. carry out this mode before putting-out-lights mode release. refer to a ?setting operation flow chart? about the details of a setup. write com data"0" in the gcram address which is not used for incorrect display prevention. [command format] lsb msb b0 b1 b2 b3 b4 b5 b6 b7 1st byte * * * * 0 0 1 0 : selects a gcram data write mode. (1st) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 2nd byte c0 c1 c2 c3 c4 c5 c6 c7 : specifies com data. (2nd) (written into gcram address 00h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 3rd byte c8 c9 c10 c11 c12 c13 c14 c15 : specifies com data. (3rd) (written into gcram address 00h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 4th byte c16 c17 c18 c19 c20 c21 c22 c23 : specifies com data. (4th) (written into gcram address 00h) c0 (lsb) to c23 (msb): grid control data (24 bits) *: don?t care note: to specify additional grid control data, specify the grid control data as shown below. the gcram addresses are automatically incremented. the second byte to the fourth byte (for grid data) are treated as a single piece of element and the byte-byte t doff can be 200 ns. pedl9204-02 oki semiconductor ML9204-XX 25/41 lsb msb b0 b1 b2 b3 b4 b5 b6 b7 2nd byte c0 c1 c2 c3 c4 c5 c6 c7 : specifies com data. (5th) (written into gcram address 01h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 4th byte c16 c17 c18 c19 c20 c21 c22 c23 : specifies com data. (7th) (written into gcram address 01h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 2nd byte c0 c1 c2 c3 c4 c5 c6 c7 : specifies com data. (71st) (written into gcram address 17h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 4th byte c16 c17 c18 c19 c20 c21 c22 c23 : specifies com data. (73rd) (written into gcram address 17h) with the above operations, com data of up to 24 digits are set. to set other com data at gcram addresses 00h and later, specify dummy symbol data at gcram addresses 18h to 1fh (to automatically increment the gcram address and set the gcram address to 00h). [gcram addresses (digit positions) and com positions] gcram address (hex) 1(00) 2(01) 3(02) 22(15) 23(16) 24(17) com1 c0 c1 c2 c21 c22 c23 com2 c0 c1 c2 c21 c22 c23 com3 c0 c1 c2 c21 c22 c23 com4 c0 c1 c2 c21 c22 c23 com5 c0 c1 c2 c21 c22 c23 com20 c0 c1 c2 c21 c22 c23 com21 c0 c1 c2 c21 c22 c23 com22 c0 c1 c2 c21 c22 c23 com23 c0 c1 c2 c21 c22 c23 com24 c0 c1 c2 ? ? ? ? ? c21 c22 c23 pedl9204-02 oki semiconductor ML9204-XX 26/41 [gcram output example] 1. when 4-digit of the 9-digit display requires an output current of 40 ma pedl9204-02 oki semiconductor ML9204-XX 27/41 2. when only one digit of the 22-digit display requires an output current of 60 ma pedl9204-02 oki semiconductor ML9204-XX 28/41 5. display duty set (writes display duty value to duty cycle register) display duty adjusts brightness in 1024 stages using 10-bit data. when power is turned on or when the reset signal is input, the duty cycle register value is ?0?. always execute this instruction before turning the display on, then set a desired duty value. [command format] d0 (lsb) to d9 (msb) : display duty data (10 bits: 1024 stages) * : don?t care [relation between setup data and controlled com duty] hex d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 com duty 000 0 0 0 0 0 0 0 0 0 0 0/1024 001 1 0 0 0 0 0 0 0 0 0 1/1024 002 0 1 0 0 0 0 0 0 0 0 2/1024 3be 0 1 1 1 1 1 0 1 1 1 958/1024 3bf 1 1 1 1 1 1 0 1 1 1 959/1024 3c0 0 0 0 0 0 0 1 1 1 1 960/1024 3c1 1 0 0 0 0 0 1 1 1 1 960/1024 3ff 1 1 1 1 1 1 1 1 1 1 960/1024 the state when power is turned on or when reset signal is input. d0 d1 * * 1 0 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects display duty set mode and sets duty value (lower 2 bits) d2 d3 d4 d5 d6 d7 d8 d9 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : sets duty value (upper 8 bits) (1st) pedl9204-02 oki semiconductor ML9204-XX 29/41 6. number of digits set (writes the number of display digits to the display digit register) the number of digits set can display 9 to 24 digits using 4-bit data. when power is turned on or when a reset signal is input, the number of digit register value is ?0?. always execute this instruction to change the number of digits before turning the display on. [command format] k0 (lsb) to k3 (msb) : number of digit data (4 bits: 24 digits) * : don?t care [relation between setup data and controlled com] * when the number of com is one at 1 digit hex k0 k1 k2 k3 number of digits of com hex k0 k1 k2 k3 number of digits of com 0 0 0 0 0 1-24(com1 to 24) 0 0 0 0 1 1-16(com1 to 16) 1 1 0 0 0 1-9(com1 to 9) 1 1 0 0 1 1-17(com1 to 17) 2 0 1 0 0 1-10(com1 to 10) 2 0 1 0 1 1-18(com1 to 18) 3 1 1 0 0 1-11(com1 to 11) 3 1 1 0 1 1-19(com1 to 19) 4 0 0 1 0 1-12(com1 to 12) 4 0 0 1 1 1-20(com1 to 20) 5 1 0 1 0 1-13(com1 to 13) 5 1 0 1 1 1-21(com1 to 21) 6 0 1 1 0 1-14(com1 to 14) 6 0 1 1 1 1-22(com1 to 22) 7 1 1 1 0 1-15(com1 to 15) 7 1 1 1 1 1-23(com1 to 23) the state when power is turned on or when reset signal is input. k0k1k2k30110 b0 b1 b2 b3 b4 b5 b6 b7 1st byte l s bm s b : selects the number of digit set mode and specifie s the number of digit value pedl9204-02 oki semiconductor ML9204-XX 30/41 7. all display lights on/off set (turns all display lights on or off) all display lights on is used primarily for display testing. all display lights off is primarily used for display blink and to prevent malfunction when power is turned on. [command format] l, h : display operation data * : don?t care [set data and display state of seg and ad] l h display state of seg and ad 0 0 normal display 1 0 sets all outputs to low 0 1 sets all outputs to high 1 1 sets all outputs to high * priority is given to an all-points light command. l h * * 1 1 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects all display lights on or off mod e pedl9204-02 oki semiconductor ML9204-XX 31/41 c. key scan stop this command stops key scanning and makes row1 to row5 outputs ?low? and the int output ?low?. [command format] lsb msb b0 b1 b2 b3 b4 b5 b6 b7 1st byte * * * * 0 0 1 1 : stops key scanning. *: don?t care d. key data output this command puts the pin in the output mode and causes the pin to output the scanned switch data. the di/o pin outputs 42-bit switch data at the rise of a clock. when the cs pin goes high, the di/o pin enters the output mode. ?r1, r2, r3 = 0? means turning a control knob clockwise. ?r1, r2, r3 = 1? means turning a control knob counterclockwise. contact count bits are q11(lsb) to q13(msb), q21(lsb) to q23(msb), and q31(lsb) to q33(msb). [command format] lsb msb b0 b1 b2 b3 b4 b5 b6 b7 1st byte * * * * 1 0 1 1 : outputs key data. *: don?t care [col input and row output key-switch matrix] col1 s11 s21 s31 s41 s12 s22 s32 s42 s13 s23 s33 s43 s14 s24 s34 s44 s51 s52 s53 s54 s55 col2 col3 col4 s15 s25 s35 s45 col5 row1 row2 row3 row4 row5 s16 s26 s36 s46 col6 s56 pedl9204-02 oki semiconductor ML9204-XX 32/41 [output data format] output data: 42 bits 5 6 push switch data: 30 bits encoder switch data: 12 bits bit 1 2 3 4 5 6 7 8 9 10 11 12 output data s11 s12 s13 s14 s15 s16 s21 s22 s23 s24 s25 s26 bit 13 14 15 16 17 18 19 20 21 22 23 24 output data s31 s32 s33 s34 s35 s36 s41 s42 s43 s44 s45 s46 bit 25 26 27 28 29 30 31 32 33 34 35 36 output data s51 s52 s53 s54 s55 s56 r1 q11 q12 q13 r2 q21 bit 37 38 39 40 41 42 output data q22 q23 r3 q31 q32 q33 sij: i = row1 to 5; j = col1 to 6 sij = 1: switch on sij = 0: switch off pedl9204-02 oki semiconductor ML9204-XX 33/41 keyscan keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. the int pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the int pin can be used as an interrupt signal. [keyscan timing and cycles] depress/release keyscan stop 1 keyscan cycle row1 row2 row3 row4 row5 in t keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. to stop keyscanning, it is required to select the keyscan stop mode once again. ks ks ks depress release keyscan depress keyscan in t cs ks: keyscan stop mode pedl9204-02 oki semiconductor ML9204-XX 34/41 the rotary encoder switch function as figure 1 shows, the rotary encoder switch circuit is consisted of phase detection, interrupt generation, up/down counter, direction latch and parallel-in serial-out shift register. the rotary encoder switch circuit 1. phase detection 1-1. clockwise rotation the input a and b have a chattering absorption circuit of 256 s period. when signal a and b input as shown below, the phase detection circuit outputs up signal after the chattering absorption period. at this time, the output int also goes to high level, so this signal can be used as an interrupt. the int stays high level until the keyscan stop mode is selected. up (internal) b a int chattering absorption time the input and output timing in the c ase of clockwise rotation phase detection up down b q3 q2 q1 a up/down counter p-in/s-out shift register r1 direction latch interrupt generation for int output data pedl9204-02 oki semiconductor ML9204-XX 35/41 1-2. counterclockwise rotation when signal a and b input as shown below, the phase detection circuit outputs down signal after the chattering absorption period. at this time, the output int also goes to high level. the int stays high level until the keyscan stop mode is selected. down (internal) b a int chattering absorption time the input and output timing in the c ase of c ounterclockwise rotation 2. up/down counter when the up/down counter is input up, it counts up and when it is input down, it counts down. but if the up/down counter is incremented beyond ?111?, it stays ?111?. b q1, q2, q3 a 100 010 110 001 101 011 111 111 counter overflow 3. direction latch when the direction latch is input down the output r1 goes ?1?. but if the up pulse is input and the count value changes to a positive value, the output r1 goes to ?0?. 100 q1, q2, q3 100 100 b a 010 000 010 r1 direction latch pedl9204-02 oki semiconductor ML9204-XX 36/41 f. standby mode set (display all switched off and an oscillation stopped) standby mode realizes low power consumption of vdd, vseg, and vcom by all switching off a display, stopping an oscillation of an external (com is fixed to low) oscillation child, and stopping internal operation completely. all display lights off is primarily used for display blink and to prevent malfunction when power is turned on. * if a reset signal is inputted during standby mode execution, standby mode is canceled, and keep in mind it that all states will be initialized. [command format] * : don?t care [release standby mode] release in standby mode is performed in falling of cs . (an oscillation child's oscillation is started) data input will become possible if an oscillation is stabilized. (please return brought-down cs high-level before data input) when you display after standby mode release since it is all putting out lights although the setting state is held, please cancel all putting-out-lights modes (in usual mode). * please do not input a shift clock into cp until an oscillation is stabilized. (data will be given) trson (oscillation standup time) changes with oscillation children who use it. please make reference an oscillation child's data to be used. * * * * 1 1 1 1 1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : standby mode is specified. osc0 0.9vp-p vp-p t rson set it as 200nsec. c s c p lsb msb 1st byte * may not place the section. da b0 b1 b2 b3 b4 b5 b6 b7 data input oscillation stop state standby release, standby section usually, a state of operation (all putting-out-lights states) standby state oscillation unstable state (oscillation standup time) oscillation stable state oscillation start pedl9204-02 oki semiconductor ML9204-XX 37/41 setting flowchart (power applying included) apply v seg /v com all display lights off number of digits setting display duty setting cgram_a or b data write mode (with address setting) cgram_a or b character code another ram to be set? releases all display lights off mode adram_a or b data write mode adram_a or b character code dcram_a or b data write mode dcram_a or b character code dcram is character code write ended? select a ram to be used status of all outputs by rese t display operation mode no no no yes yes yes yes end of setting apply v dd no address is automatically incremented address is automatically incremented address is automatically incremented cgram is character code write ended? adram is character code write ended? r ese t execution gcram data write mode gcram code no yes address is automatically incremented gcram write ended? pedl9204-02 oki semiconductor ML9204-XX 38/41 power-off flowchart application circuit *1 the v seg and v com voltages depend on the fluorescent display tube used. adjust the value of the constants r and zd to the v seg and v com voltages used. *2 the wiring trace between the osc0 pin and the resonator should be kept as short as possible, and the gnd traces should be provided along both sides of the wiring trace. *3 adjust the capacitance of the capacitor depending on the type of the oscillator used. (refer to the data of oscillator used.) display operation mode turn off v dd turn off v seg /v com 24 35 35 v dd mcu v dd gnd output port 2 r zd v seg / v com crystal oscillation or ceramic oscillation l-gnd d-gnd osc0 osc1 5 x 7 dot matrix fluorescent display anode (segment) anode (segment) grid (digit) anode (segment) v seg ML9204-XX com1-24 sega1-a35 segb1-b35 r eset v dd di/o cp c s ada,adb v com int *1 *2 *3 5x6key matrix and rotary switch c ol1 - 6 row1-5 b1-3 a1-3 pedl9204-02 oki semiconductor ML9204-XX 39/41 package dimensions qfp128-p-1420-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.19 typ. 5 rev. no./last revised 4/nov. 28, 1996 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm) pedl9204-02 oki semiconductor ML9204-XX 40/41 revision history page document no. date previous edition current edition description pedl9204-01 jan. 8, 2003 ? ? preliminary edition 1 pedl9204-02 oct. 12, 2004 4 4 pin description added pedl9204-02 oki semiconductor ML9204-XX 41/41 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifically authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and n ecessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2004 oki electric industry co., ltd. |
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